Using Parity to Detect Memory Errors in Stratix Devices
Altera ® Stratix
TM devices feature the TriMatrix
TM memory architecture, which is composed of three different-sized embedded RAM blocks. TriMatrix memory includes the 512-bit M512 blocks, the 4-Kbit M4K blocks, and the 512-Kbit MegaRAM
TM blocks. TriMatrix memory blocks support a parity bit for each storage byte. The parity bit, along with internal logic elements (LEs), can implement parity checking for error detection to ensure data integrity. The parity generation and control logic is implemented outside the TriMatrix memory blocks, in the LEs. This white paper describes how parity can be used to detect errors and also illustrates one of the many different ways to do so: by using the Parity Detection Circuit design example.
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