The Automated Chip Creation methodology provided by Talus provides a revolutionary approach to the implementation of large digital IC designs. Talus allows the physical implementation portion of the design to commence earlier in the flow, yet it requires only one or two physical implementation engineers per design, which means that overall cost of the design can be reduced by 30 percent to 50 percent and the remaining physical design engineering resources can be deployed to other projects.
The fast turnaroun time provided by Talus results in predictability and early feedback on achievable performance. This also allows system designers to perform "what-if" explorations on function versus cost with regard to the physical implementation. Furthermore, it allows design teams to spend more time experimenting at the architectural stage of the design, and to take full advantage of modern electronic system level (ESL) design tools. And the fact that the turnaround time required for a physical implementation to address functionality changes in the RTL can be reduced by 50 percent to 90 percent means late-stage changes to the design requirements can be accommodated without delaying the project schedule.
Last but certainly not least, Talus-generated implementations offer better performance in terms of timing, area, power consumption, and signal-integrity compared to conventional flows (for example, one Talus-generated reference design consumed 17percent less silicon real estate as compared to a physical implementation generated using a conventional flow). This means that the cost of manufacturing can be significantly reduced.
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