Three Paths to Improved Critical Dimension Control for Patterning 200nm to 100nm Transistor Gates

In this paper we present the results of applying three different approaches to improving critical dimension control: (1) CD control improvements for 200nm isolated lines using DUV lithography (k1=0.34) with assisting features, (2) CD control improvements for 140nm patterns using 248nm DUV lithography (k1=0.24) with alternating phase-shifting masks, and finally (3) CD control improvements for 100nm patterns using i-line and 248nm DUV lithography (k1= 0.17) with spacer-gate processes.

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