Turning Algorithms into the Right Hardware Architectures for ASICs

This paper describes the methodology for using Cadence signal processing worksystem (SPW) and Cadence hardware design system (HDS). SPW with HDS provides system level simulation, hardware architecture modeling, and efficient paths to synthesis and functional ASIC/IC verification for signal processing algorithms. The combination of these capabilities provides high productivity and first-time implementation success for signal processing product design.

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