The CoreConnect Bus Architecture

This white paper describes CoreConnect Bus Architecture, a 32-, 64-, 128-bit core on-chip bus standard that eases the integration and reuse of processor, system, and peripheral cores within standard product and custom system-on-a-chip (SOC) designs. Topics include Processor Local Bus, PLB Bus Transactions, PLB Cross-Bar Switch, On-Chip Peripheral Bus, OPB Bridge, OPB Implementation, DCR Bus, Design Toolkits, and comparison to other bus architecture types. Block and timing diagrams are included.

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