Top-Level Validation of System-on-chip in Esterel Studio

The paper presents a new tool-supported methodology for System on Chip Top-Level Validation (TLV). The addressed problem is the systematic validation of IP interaction to ensure correct global functional behavior of a SoC design, assuming that each IP has been individually validated. The goal is to generate functional tests for the final design that cover the interaction behavior in a systematic, well-defined, and complete way. The typical problem to be found is incorrect inter-IP data flow due to misconfiguration or missynchronization of IPs.

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