The Need for a High-Bandwidth Memory Architecture in PLDs

One of the challenges faced by engineers designing communications equipment is that memory devices were adopted from PC computer platforms. These devices, although inexpensive and easy to source, are suboptimal for communication systems because they were designed with a different end system in mind. SDRAM memory is a good example of a "borrowed" PC technology. Fundamentally, SDRAM memory was designed for microprocessor storage, not to accept TCP/IP packets travelling at 10 gigabits per second (Gbps) through very high-performance switching equipment. Although discrete memory suppliers introduced new architectures with increased bandwidth such as double data rate (DDR), zero-bus turnaround (ZBT), and quad data rate (QDR), these architectures have not kept pace with the performance demands of transmission media standards such as OC-48 and OC-192. Since these discrete devices formerly were the only source of system memory, they defined the bottleneck in the system. The industry adapted by developing sophisticated memory architectures embedded within programmable logic devices (PLDs). Over the last several years, the memory architectures in PLDs have become as complex as many ASIC system designs, including application-optimized features such as dual-port, mixed-width, and parity bits.

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