The Evolution of High-Speed Transceiver Technology

The Internet revolution has led to a massive increase in data traffic. This trend is set to continue; over the next few years and it is likely that 95% of all communication traffic will shift to data. The need to support high bandwidth traffic has required that equipment performance grow at an exponential rate. WAN equipment which only two years ago operated at speeds of OC-48 (2.5Gbps) now runs at speeds up to OC-192 (10Gbps), and the development of OC-768 equipment (40Gbps) utilizing System Packet Interface-5 (SPI-5) and SERDES Framer Interface-5 (SFI-5) is already underway. System performance has also increased to support this infrastructure. Backplane and chip-to-chip interfaces supporting multiple serial lines of data are replacing parallel bus implementations in many applications. For example the 10 Gigabit Ethernet XAUI protocol is becoming increasingly popular in backplane applications, where four aligned channels of 3.125 Gbps collectively provide a backplane data rate of 10 Gbps. Increases in performance have led semiconductor vendors to develop products capable of handling data rates in excess of 40 Gbps. This in turn has caused a continued evolution from single-ended I/O to differential signaling and the use of serialization and embedded clock recovery. The latest deployed systems use transceivers capable of supporting I/O speeds up to 3.125 Gbps. At these speeds the transceiver block must include more efficient clocking circuitry employing encoding/decoding, clock rate matching, and alignment techniques to ensure accurate transmission of data through multiple media. This white paper discusses the evolution of this transceiver technology and describes areas of application where it may be used.

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