The Need for Dynamic Phase Alignment in High-Speed FPGAsWith the explosion of data, voice, and video traffic across many markets, FPGAs are now being used in applications that require data transmission speeds in the gigabits per second (Gbps) range and beyond. Well suited to these applications, FPGAs provide the flexibility needed to handle the rapidly evolving standards that characterize this design space. Programmable logic solutions allow developers to rapidly bring their products to market by avoiding the long development times, high non-recurring engineering costs (NREs), and inventory risks associated with custom solutions. FPGAs offering embedded silicon implementations of dynamic phase alignment (DPA) represents a significant advancement in the capabilities of programmable logic, and provides an important complement to high-speed clock-data recovery (CDR) transceiver technology for multi-gigabit signaling. This white paper describes the advantages of DPA technology and the benefits of incorporating it into FPGA products. When building high-performance products, system developers face significant challenges in maintaining the precise timing and signal integrity required to reliably sustain multi-gigabit data rates. Differential signaling standards like LVDS aid in this effort by providing common mode rejection, which greatly reduces the effects of electrical noise. Clock-data recovery (CDR) transceiver implementations combine the clock and data into a single signal, thus ensuring simultaneous arrival at their destination. However, a number of chip-to-chip interface standards are source-synchronous, which requires a clock from the transmission source that is separate from the data. For these source-synchronous interfaces, keeping the clock and data signals in phase can be difficult when confronting board and device-level effects such as skew, jitter, and noise. In order for FPGAs to maintain their value in high data-bandwidth applications, they require an integrated solution to address this design situation.
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