The Effects of Hierarchy on Debug time in Formal Verification Tools with and without Decompositional Verification

With ever reduced times to market and increasing design complexity caused by the system-on-chip (SoC) era of design technology more design teams are now relying on Formal Verification, especially equivalence checking, as an essential part of their design flow to ensure obtaining correct silicon on time. Equivalence checking is the process that proves, by hidden formal mathematics, the property that all outputs of two revisions of a design are functionally equivalent for all combinations of inputs. Today's equivalence checking tools cope with the complexity of today's designs in one of two ways. One method is to decompose the design into multiple blocks and verify each block sequentially. The other method is to tune the equivalence checking tool for optimum memory utilization, so that the entire design can be verified at once. This paper examines the advantages and disadvantages of both methods and shows how Mentor's FormalProTM equivalence checker enables the best possible use of these methods to reduce debug time.

View Entire Paper | Previous Page | White Papers Search

If you found this page useful, bookmark and share it on: