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Taking Advantage of Delay Correlation Effects to Design High Speed Digital Circuits

Getting the best performance out of your silicon means squeezing every little bit of extra time out of your circuit. One way to improve system speed is to perform a delay correlation analysis during the early stages of your design and optimize your circuit to take advantage of the delay tracking between gates. The variation in delays between gates within a given IC is smaller than between gates on different ICs of the same type because of process and temperature variations across the ICs. Delay correlation between on-chip gates gives designers the ability to build circuits that can run faster than might seem possible when performing timing analysis using the worst case across-chip min/max delays provided by most chip manufacturers. Experienced digital designers have been taking advantage of delay correlation for many years to build high speed circuits, but until recently there has been no tool for systematically designing a circuit that optimizes system timing by accounting for delay correlation effects. SynaptiCAD's WaveFormer program enables a designer to interactively specify and analyze delay correlation effects on system timing as his design takes shape, allowing the designer to visualize the true timing bottlenecks in his system and make system changes to achieve optimal system performance.

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