Substrate Noise Analysis of Mixed-signal ICs

The availability of nanometer process technologies (0.25Ám and below) gives designers the opportunity to integrate multiple system components onto a single chip. This pays dividends in enhanced performance, as well as dramatically-reduced area, power, and overall system cost. However, system-on-a-chip (SoC) design is very challenging, especially when analog and digital components are integrated onto the same chip. Whenever digital circuits switch, they inject noise into the common substrate, and this can easily corrupt sensitive analog signals. As feature sizes decrease and clock frequencies increase, the amount of substrate noise created by digital switching increases dramatically. Consequently, substrate noise is a key cause of inexplicable design failures and poor yields of mixed-signal SoC designs.

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