Signal and Design Integrity
As processes shrink and frequencies increase, designers must now address the problems created by second order physical effects, which were generally ignored in the past. These problems can be divided into two main categories—signal integrity and design integrity. Signal integrity (SI) problems are generally related to timing and can be detected during the design or test phase of the chip. It is becoming impossible for designers to achieve timing closure without considering signal integrity effects. Design integrity problems are related to reliability of the chip in the field, and if not considered, the chip can fail prematurely. This white paper discusses both categories of problems and the proposed solution developed by Cadence Design Systems, Inc. to address these problems.
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