The global electronics industry was once characterized by neatly stacked vertical companies. For example, ASIC vendors historically created their own process-specific libraries, developed their own design tools and sign-off methodologies, and operated their own foundries. That all changed over the last decade, a period in which many of these companies spun out large parts of their businesses and divested themselves of ever more expensive manufacturing capacity. The result is the current industry landscape -- a horizontal network of design chain suppliers spread around the globe. For a time, this disaggregation brought desired business efficiencies, but with the advent of nanometer process nodes, cracks inevitably began to appear in IC design supply chain. Whereas above 130-nanometer companies could afford to ignore many second- and third-order effects such as noise and crosstalk, today’s designs require deeper collaboration among the various industry players in order to overcome the effects of physics -- especially on signal integrity, dynamic and leakage power consumption, and manufacturability.
Recognizing this need to cooperate more closely on nanometer design issues, industry leaders Applied Materials, ARM, Cadence and TSMC formed the Silicon Design Chain (SDC) Initiative. Combining their expertise, these companies have established a charter to drive programs designed to address the top issues facing their customers as they adopt advanced process technologies.
In 2004, members of the SDC identified power management as the most critical design consideration for high-performance wired devices due to leakage issues and potentially expensive cooling and packaging costs, as well as lower reliability associated with high levels of on-chip power dissipation. During the following year and one half, the SDC member companies executed the first phase of an ongoing collaborative project to address the problem of power management. In this first phase, understanding that the introduction of new design techniques must be managed step by step to ensure success, the team chose to focus on using four power-lowering techniques: automatic multi-threshold leakageperformance optimization, static voltage scaling, clock gating and a new accurate delay prediction methodology that works across multiple voltage domains. The result was a design approach that dramatically reduced both dynamic and leakage power. The SDC team validated this low power solution in silicon with the successful implementation of a chip based on the ARM1136JF-STM processor module. The device, aimed at mobile and wireless applications, yielded a greater than 40% savings in power consumption.
Phase I of the low power initiative, focused on several of the most obvious methods for power management. In Phase II, ARM and Cadence are working on a additional methods to attack leakage more aggressively. For example, to lower leakage or dynamic power in circuits, the best approach involves shutting down circuitry when it is not being used. This technique is called power gating. Another approach to lowering dynamic power consumption involves intelligently lowering the operating frequency of the circuit when high clock speeds are not required by the function the circuit needs to perform. This approach is termed dynamic voltage scaling because the device will have multiple operating frequencies. Both of these techniques will be fully explored in phase II along with the need to address test and formal verification for low power circuits.
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