The movement towards serial chip to chip and backplane interconnects continues at a frantic pace, particularly in the communications and storage arena. Standardization forums such as the OIF, RapidIO TA, PCI-SIG, OBSAI and CPRI have solidified their work and various packet-based protocols are in the process of being adopted by system and chip vendors. In addition to these emerging protocols, there is also a broad installed base of more mature serial-based protocols such as GbE, 10G Ethernet, SONET and Fibre Channel that must be addressed as they undergo a facelift to accommodate the multi-protocol nature of the network.
As the PHY and protocol layers of these new standards are being established and work continues to upgrade existing technology in the field, system vendors now have to decide how best to transmit these various protocols over existing transmission infrastructures, both inter- and intra-board.
Although each protocol is unique, one thing that they all have in common is a layered protocol stack. However, all protocol stacks are not created equal: their implementation can vary greatly from one layer to the next. Typically, the physical layer consists of fixed functionality that is common to multiple packet-based protocols, while the upper layers tend to be more customizable. The dynamic of upper layer functionality is necessitated by both the natural evolution that takes place when dealing with an emerging standard as well as the desire of system vendors to create their own "value add" via proprietary functionality. In either case, the value of programmability for implementation of these serial standards means a SERDES-based FPGA solution will remain a necessity for the foreseeable future. Figure 1 shows the functional partitioning of the physical and the upper layers of the protocol stacks.
This white paper examines the implementation of these multi-protocol standards and their associated stacks, and discusses why they are ideally suited to an FPGA-based SERDES implementation such as the LatticeSC family of FPGA devices.
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