SI Sign-off Verification

The number of silicon failures caused by undetected and unresolved signal integrity (SI) violations is rising dramatically. This is because SI effects are becoming increasingly significant as deep sub-micron (DSM) geometries continue to shrink and functional density the number of transistors on a device continues to rise. This paper introduces some of the more common SI effects that need to be accounted for during implementation and - to a far greater level of accuracy - during post-layout sign-off verification. Also discussed is an innovative new approach to SI sign-off verification.

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