SystemC Standard

The emergence and great popularity of system-on-chip (SoC) designs has brought with it a variety of suggestions for a single language that can describe all of the functional requirements for those highly complex designs. This paper takes a look at the requirements for system-level design languages and evaluates what it will take for any of these languages to be successful.

The hardware design world standardized on two languages for hardware design: VHDL and Verilog. Lately, there has been a growing effort to find a language that can describe the hardware at a much higher level. Also, as software has become a much more important part of all electronic systems, sometimes as much as 90% of the design is software, efforts have been made to find a system-level design language that can work for both hardware and software high-level descriptions.

The driving forces behind the urge towards a system-level design language are the simultaneous increase in design complexity, with multi-million gate designs, and increase in pressure to get designs out faster with first-time design success. System-level design is required to get new designs to market fast and to manage design complexity.

Because this is a new market, there are a number of suggestions for system-level design languages. This paper takes a serious look at system-level design languages and what it will take for a language to succeed in this fast-growing market.

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