Standards for System-Level Design: Practical Reality or Solution in Search of a Question?

The authors address the issue of standards development for the system-level design space. System-level design IP re-use standards are key to the future of the VSIA. However, the concept of system-level standards has its share of sceptics: what role can standards play in this developing market segment? In response we present an overview of three standards in the system-level VC integration space, and describe two distinct industrial case studies to support their practicality.

Three factors drive the need for standards within the design and EDA industry. These are the need for: (1) common communication principles, (2) common design formats, and (3) a unified approach to design-quality measurement and assurance. Standardising communication permits straightforward connection of tools (e.g., via APIs), virtual components (VC) (e.g., via bus standards), or complete SoC designs (e.g., telecom standards). Standardisation of design formats ensures comprehensive design-property encapsulation within a small set of alternatives (e.g., RTL synthesizable subset of VHDL or Verilog). Finally, quality-based standards must help resolve an industry-wide design-quality issue. For the VSIA, the quality issue is the guarantee of SoC design integrity while ensuring fast integration of VCs from multiple sources.

To ensure "design quality" in the rapidly developing system-level design space, standards must help to align existing technology and design principles with emerging concepts. They link the fundamental principles developed in academia to the industrial needs of: a) the handling legacy-components, b) catering to customer risk-tolerance, and c) understanding how the flurry of new system-level tools enhance existing design flows.

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