Spartan-II Family as a Memory Controller for QDR-SRAMs
The explosive growth of the Internet is boosting the demand for high-speed data communication systems. In order to increase memory bandwidth significantly for future high-performance communication applications, Cypress Semiconductor, Integrated Device Technology, Inc. and Micron Technology have jointly defined and developed a new SRAM architecture referred to as the Quad Data Rate (QDR) SRAM technology. FPGAs are ideal to implement the control and interface logic, which ties the CPUs to the QDR SRAMs. The Spartan-II FPGA, with its unique and extensive features is an ideal memory controller interface for the QDR SRAM. Spartan-II offer more than 100,000 system gates at under $10 and are the most cost-effective programmable logic devices (PLD) solution ever offered.
View Entire Paper | Previous Page | White Papers Search
If you found this page useful, bookmark and share it on:
Embedded Star Newsletter
Don't have time to visit Embedded Star everyday? Then sign up for our free newsletter. We'll send you an email when we have something to share with you. Your email address will be kept confidential and we will not share, sell, or rent it to anyone. You can unsubscribe at any time by clicking a link in the email.
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
