RTL Rule Checking Enforces Best Practices for Using Embedded Programmable Logic in ASICs and ASSPs

Embedded programmable cores also raise the specter that designers may now have to design for two different architectures: the traditional ASIC architecture they are used to and the architecture of the programmable logic core. This paper looks at how architectural differences in standard ASIC design blocks and embedded programmable logic cores require different design approaches in the RTL code and how RTL rule checking can help enforce Best Practices in RTL design for embedded programmable logic in ASICs and ASSPs.

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