Reducing ASIC Respins Using FormalPro Equivalence Checker
Formal Verification is a very important and critical task in the verification process for ASICs and ICs. It dramatically reduces the time required to verify a design from weeks to days. More importantly, formal verification can play a critical role in reducing the number of ASIC respins required in a project. By reducing or eliminating ASIC respins, project teams can save hundreds of thousands - even millions - of dollars in product costs alone. Furthermore, huge economic benefits can be realized through reducing a product's time-to-market by between six and twelve months. This white paper discusses the main causes of ASIC respins, and how formal verification provides the optimum solution for reducing or eliminating respins. Mentor Graphics' formal verification solution, FormalPro
TM, describing its capabilities for verifying multi-million gate designs as one, and its highly advanced debug capabilities that enable engineers to save weeks in verifying their designs. Finally, an analysis of the cost benefit of formal verification is provided, including examples of cost savings that can be achieved.
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