RocketIO Transceiver Bit-Error Rate Tester
This application note describes the implementation of a RocketIO transceiver bit-error rate tester (BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s) between two RocketIO multi-gigabit transceivers (MGT) embedded in a single Virtex
TM-II Pro FPGA. To build a system, an IBM CoreConnect
TM infrastructure connects the PowerPC
TM405 processor (PPC405) to external memory and other peripherals using the processor local bus (PLB) and device control register (DCR) buses. The reference design uses a two-channel Xilinx bit-error rate tester (XBERT) module for generating and verifying high-speed serial data transmitted and received by the RocketIO transceivers. The data to be transmitted is constructed using pseudorandom bit sequence (PRBS) patterns. The receiver in XBERT module compares the incoming data with the expected data to analyze for errors. The XBERT supports several different types of user selectable PRBS patterns. Frame counters in the receiver are used to track the total number of data words (frames) received, and total number of data words with bit errors. The processor reads the status and counter values from the XBERT through the PLB Interface, then sends out the information to the UART.
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