RapidIO: An Embedded System Component Network Architecture

This paper describes RapidIO, a high performance low pin count packet switched system level interconnect architecture. The interconnect architecture is intended to be an open standard which addresses the needs of a variety of applications from embedded infrastructure to desktop computing. Applications include interconnecting microprocessors, memory, and memory mapped I/O devices in networking equipment, storage sub-systems, and general purpose computing platforms. This interconnect is intended primarily as an intra-system interface, allowing chip to chip and board to board communications at giga-byte per second performance levels. Supported programming models include globally shared distributed memory and message-passing. In its simplest form, the interface can be implemented in an FPGA end point. The interconnect architecture deŽnes a protocol independent of a physical implementation. The physical features of an implementation utilizing the interconnect are deŽned by the requirements of the implementation, such as I/O signalling levels, interconnect topology, physical layer protocol, error detection, etc. The interconnect is deŽned as a layered architecture which allows scalability and future enhancements while maintaining compatibility.

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