Logic designers have focused their verification efforts on functionality and have developed tools to assure that, functionally, the design works right the first time. Logically, however, verifying a memory design is quite simple. It either stores a '1' or a '0'. In embedding memories, it is the manufacturability (test, yield, repair) and field reliability (field repair, Soft Error Rate or SER) that are of importance. As the percentage of die area dedicated to embedded memories increases with each new process generation, memories are becoming the most important factor driving the quality of SoCs. Unless quality issues are addressed, the benefits of embedding large memories on chips will be negated. During manufacture, defects on the silicon wafer introduce errors that must be corrected. Without correction, the IC must be discarded. Traditionally, memory testing and repair on these SoCs during manufacturing depends on identifying and disabling the unique row or column with the defect using laser repair. During field operation, system designers need to ensure that "soft errors" due to alpha particles or cosmic rays will not cause the system to fail. This presentation describes Transparent Error Correction (TEC), a new technique that simplifies testing by eliminating the need for laser repair and improves field reliability. The result is improved quality for the end application at a reduced cost during both the manufacture and field-use.
Don't have time to visit Embedded Star everyday? Then sign up for our free newsletter. We'll send you an email when we have something to share with you. Your email address will be kept confidential and we will not share, sell, or rent it to anyone. You can unsubscribe at any time by clicking a link in the email.
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
