Parallel Simulation of Chip-Multiprocessor Architectures
The complexity of parallel systems has increased both the need for comprehensive simulation and the computation time required to perform the simulations. Chip-multiprocessor (CMP) architectures are particularly susceptible to this effect, combining the requirements of a microprocessor simulator with that of a parallel system. In this paper, a portable, distributed simulator for CMPs is presented based on the Message Passing Interface (MPI) that is designed to run on a cluster of workstations. Because the simulator itself is a complex application, microbenchmark-based evaluation is used to compare parallelization algorithms and interconnects for use in the parallel simulator while identifying potential bottlenecks. The best combination is shown to yield speedups of up to 16 on a 9-node cluster of dual-CPU workstations.
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