In today's higher performing SoCs, clock gating is increasingly becoming an inseparable part of the system-on-chip design technique due to strict chip power requirements. In theory, clock-gated designs can achieve both lower power consumption and improved timing performance compared to similar non-clock-gated designs. Typically, since not all circuits are in use all of the time, this variance in unused assets is an opportunity to reduce power dissipation.
The biggest power savings of clock gating will be for dataflow-intensive designs. Collectively, the benefit of clock gating in portable electronics systems, for example, can be measured in longer battery life, as well as improved reliability and less costs associated with heat reduction.
Clock gating has an impact on static timing analysis (STA), clock tree synthesis (CTS), design-for-testability (DFT) and dynamic power analysis. Previously performed manually by chip designers, the entire process of clock gating is now automated with a suite of design tools and methodologies offered by Toshiba. In customer designs, clock-gating techniques can significantly reduce the chipís dynamic power compared to similar non-clock gated designs.
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