We have developed an 80nm poly gate patterning process for 0.13 micron VLSI manufacturing using 248nm lithographywith double-exposure phase-shifting technique. We show that: Systematic intra-field line width variation can be controlled within 6nm (3sigma), with good line-end shortening control for gate endcaps. The k1 factor is < 0.2 (80nm target gate length in 320nm pitch).
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