Processor-Based SOCs Pose New Hardware/Software Debug Challenges
Designers seeking to leapfrog the competition with superior performance at lower cost are embedding custom logic blocks and large third-party intellectual property (IP) elements into large single chip solutions. But these solutions come with some significant new development and debug issues. To unravel the hardware/software integration problems associated with complex single chip designs, a fast and accurate simulation of the final system and an effective debugging tool are needed. A new approach based on ReConfigurable Computing (RCC) technology from Axis, attacks the problem with a unique blend of simulation and hardware emulation that solves performance and debug problems simultaneously. This paper demonstrates how a new breed of verification solutions based on RCC addresses the debugging challenges of hardware and software integration.
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