Optimizing Speed vs. Size: Using the Codebalance Utility for ARM/Thumb and MIPS16 Architectures
Not all parts of a microprocessor program require high-speed performance. In some applications, a more important aspect is the size of the code in RAM or ROM. It is this requirement that dual-purpose architectures such as ARM/Thumb and 16-bits were designed to address. Thumb and MIPS16 are architecture extensions whereby an otherwise 32-bit architecture (ARM and MIPS) is enabled to process 16-bit instructions. The use of 16-bit instructions would double available RAM or ROM space if each instruction could do the same work as a 32-bit instruction. This is not always the case. In general, a 16-bit instruction is limited in the number of Op Codes it can call upon and in the number of registers and addressing modes it can reference. Thus, while each instruction can still perform a 32-bit operation, the limitations on registers, addressing and Op Codes makes the 16-bit instructions less powerful than 32-bit instructions.
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