Noise-aware Timing Analysis

Timing sign-off is where the digital design process comes to a crunch. The goal of timing analysis is to ensure that a design will operate at the required clock frequency when it is fabricated. If the chip fails to meet its performance target, designers must implement engineering change orders—ECOs—to fix reported timing problems. Designers repeat this process until the design reaches timing closure. If designers are lucky, they reach this point within just a few iterations. But as they adopt nanometer technologies (0.18µm and below), designers find that measured silicon performance varies considerably from timing tool predictions, so additional iterations are necessary at the point where they are most costly—after fabrication.

View Entire Paper | Previous Page | White Papers Search

If you found this page useful, bookmark and share it on: