Meeting High-Performance Memory Requirements for SOC Designs

As more performance and increased functionality is demanded by the market place, the bandwidth requirements for System-on-Chip (SOC) designs being developed to support new applications must also increase accordingly. This is leading to a revision of the way one looks at memory technologies, SOC architectures and memory controller architectures so as to achieve increased parallelism, increased data rates or both. This paper will cover the architectural and control methods available to meet the memory performance demands of SOC designs. Using the example of a Multi-Channel Shared Memory Processor will show how both system performance and SOC integration efficiency is enhanced versus the use of a base DDR SDRAM controller core.

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