Minimizing SOC Risk with Embedded Programmable Logic

This white paper will examine how the use of embedded programmable logic can reduce the time spent on the verification of large system chips. Since design geometries are shrinking and at the same time, chips are getting increasingly large, verification is getting to be almost impossible. Nearly as much time is taken to verify as to design. Now, a designer can put a programmable logic IP core on a multi-million gate design. By placing the "high risk" design blocks in a programmable logic core right in a system chip, the verification engineer is able to tune his silicon and make changes without having to spend months either simulating corner case conditions or building and debugging FPGA prototypes. The paper will address applications this is best suited for, such as wireless and broadband communications.

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