Modeling and Simulation of Jitter in PLL Frequency Synthesizers

A methodology is presented for predicting the jitter performance of a Phase-Locked Loop (PLL) using simulation that is both accurate and efficient. The methodology begins by characterizing the noise behavior of the blocks that make up the PLL using transistor-level simulation. For each block, the jitter is extracted and provided as a parameter to behavioral models for inclusion in a high-level simulation of the entire PLL. This approach is efficient enough to be applied to PLLs acting as frequency synthesizers with large divide ratios.

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