Low-power Synthesis Option

Because power dissipation is becoming just as important as performance and area, power analysis and optimization must be an integral part of the design methodology. The Cadence Low-power Synthesis Option (LPS) addresses low-power issues early in the design cycle. LPS explores options for lowering power at RTL, but does not make any commitments until gate level. Also, all gate-level transformations take into account power, delay, and placement information. This white paper provides an overview of the methods employed today to address low power and outlines the solution we are putting in place to create low-power designs.

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