Improving Compute Farm Throughput in Electronic Design Automation (EDA) Solutions

Functional verification of Silicon on Chip (SoC) designs can contribute to as much as 70% of design cycle times. To develop 45nm and 32nm architectures, the computational resources needed and verification times required increase exponentially over earlier levels, with verification errors leading to production "respins" — costly both in dollar terms and time to market considerations. Increasing the degree of utilization in multicore compute farms can significantly improve application throughput and speed new product introductions. IBM and eXludus recently demonstrated that MultiCore Optimizer (MCOPt) middleware can significantly improve the performance and usability of compute farms running Cadence's Incisive Enterprise Simulator by increasing CPU utilization rates, reducing I/O wait times, and eliminating memory paging. These effects lead to shorter run times for smallmemory jobs, as well as the concurrent execution and completion of large-memory jobs that otherwise would not complete. MCOPt middleware also removes the need for manual system tuning and/or user prediction of resource requirements.

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