Advanced multi-voltage domain (multi-VDD) architectures allow designers to implement large, complex SoCs that consume the lowest possible amounts of power, while delivering the required performance and functionality. Not unexpectedly, implementing a low power, multi-VDD voltage area [VA] requires careful planning and early design architecture considerations, as well as considerable analysis.
In order to maximize device performance and reliability, the design should be optimally divided into suitable voltage areas for maximum power savings through RTL power simulation. A blueprint of the initial design modules with its various level shifter / isolation cells and proper control signals is necessary. Since multi-VDD methodology allows voltages to vary in different regions, simulation is very important to make sure that the VA design function is correct. This includes the determination of correct power-on and power-off sequence between the VAs to avoid an incorrect or floating state during operation.
Once the VA design is implemented, it needs to be verified extensively for possible violations between the different power domains. Toshiba has a well-developed, low-power design flow, which utilizes several tools for proper implementation and verification of a multi-VDD voltage area design.
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