Semiconductor manufacturers face tremendous challenges in extending optical lithography to its furthest limits in order to maintain their aggressive roadmaps. Recently we have seen this result in a concerted effort to deploy 193nm lithography as quickly as possible. However, lessons learned from the insertion of 248nm lithography should remind us that introduction of a completely new process suite is not done overnight. The near-term limited availability of production-generation 193nm tools and the time needed to develop robust processes requires extending the usefulness of the current generation of 248nm lithography tools and processes.
An inevitable consequence of roadmaps outpacing the next-generation of lithography tool deployment has been the proliferation of Reticle Enhancement Technologies (RET) to bolster the drive to ever-smaller geometries and pitches. RET has been or is being deployed extensively in current high-end and early next-generation designs to provide pilot processes for the next steps down the lithography roadmap. It has been proven that RET can improve the performance of established processes and is completely backward compatible. Indeed, RET is being used for current 193nm lithography process development and will continue to be intrinsic to these processes when tools are deployed in sufficient numbers to support large-scale manufacturing volume. This gives 193nm lithography the distinction of being the first optical generation to employ RET immediately upon introduction.
One style of RET, Optical Proximity Correction (OPC), is now extensively used for high-end processes on virtually every layer. In fact, in most cases the lithographer's decision has been narrowed down from "if" OPC should be used to a choice between which style and package of OPC one wishes to use. Well-known but not as widely adopted alternatives to binary chrome-on-glass masking (BIM) are becoming increasingly accepted into more common use as well. Dark field applications (re: Via, Contact) have in addition to OPC the option of using attenuated-embedded Phase Shift Masks (a:PSM) to further improve resolution. The manufacturing of dark field a:PSM's is not a trivial task, but the challenges are not fundamental and more photomask fabrication facilities are coming on-line with processes to produce them. Critical clear field solutions (re: Poly) demand more powerful methods to increase resolution. The preferred method is hard-shifter (Levenson) Trim-Mask PSM (t:PSM). t:PSM manufacturing can be less of a challenge than a:PSM. Standard BIM photomask blanks are used in the manufacture of t:PSM's and no third material type (such asMoSi) requiring special processing need be taken into account. This paper will explore some of the primary implementation considerations for Trim-Mask PSM. There are requirements throughout the design to silicon flow that demand a cohesive and coherent implementation strategy. The interactions between Design and Design Rules, Mask Manufacturability, and Printability require close collaboration and the employment of manufacturing capable software tools for successful insertion of Trim-Mask PSM.
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