To support these new emerging markets, carriers and wireless service providers will soon need IPv6 routers that support hundreds of thousands and up to several million addresses and flows for enabling a variety of services, QoS, security and accounting for their customers.
The IPv6 address is four times longer than the current IPv4 addresses, 16 bytes versus 4 bytes, offering a virtually unlimited number of available IP addresses. The increased length poses severe implications on a router's routing and flow tables. This is of particular significance when designing high-speed switch/routers with network processors (NPUs), since NPUs typically use expensive and power-hungry classification hardware, e.g. CAMs and SRAMs, for address and flow table lookups to meet 10-Gigabit or multi-Gigabit line rate throughput.
CAMs are specialized memory chips with on-chip logic for performing fast table lookups, while SRAM are standard high-speed memory devices that normally complement the CAM by storing part of the lookup tables data.
IPv6 effectively quadruples table lookup and classification hardware requirements. When using NPU solutions that rely on CAM and SRAM for classification, the fourfold increase entails using some 40 chips generating over 100 Watts at a cost of thousands of dollars for classification hardware alone. This makes IPv6 routers extremely expensive and complex, almost to the point of being impractical.
Is there a practical solution? Let's first take a closer look at IPv6 classification requirements and review possible solutions according to three key factors that impact router designs: the system chip count, power dissipation and total cost.
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