It's About Time: Requirements for the Functional Verification of Nanometer-scale ICs

Functional verification of nanometer-scale ICs is all about effective use of time, in terms of speed and efficiency. Yet today's fragmented functional verification processes make it impossible to optimize either.

This paper assumes three levels of design hierarchy: top-level, block-level, and unit-level. Many companies have separate design and verification engineers, while others have engineers that fulfill both roles. This paper uses the terms "verification team" and "verification engineers" to denote engineers responsible for chip-level or block-level functional verification. It uses "design teams" and "design engineers" to denote engineers responsible for implementing and verifying individual units—even though these may be the same engineers.

This is an industry white paper that describes the requirements for high-speed, high-efficiency functional verification of nanometer-scale ICs.

View Entire Paper | Previous Page | White Papers Search

If you found this page useful, bookmark and share it on: