Implementation of a 3GPP Turbo Decoder on a Programmable DSP Core
Third generation (3G) portable wireless applications will require greater data rates at lower channel SNR than ever before. To enable reliable data transmission for these applications more advanced error correcting techniques are required. An error correction technique known as Turbo Coding has greater error correction capability than any other known code, and it is specified as one of the coding options in the 3GPP standard for the European 3G Universal Mobile Telecommunications System (UMTS). This paper describes the techniques required to implement a turbo decoder on a fixed-point programmable DSP. Various mathematical and approximation techniques are described that dramatically reduce the computations required. Specifically, the implementation of a turbo decoder for the 3GPP standard for UMTS is described, but these techniques can be applied to any turbo decoder. This turbo decoder has been implemented on the 3DSP Corp. SP-5 SuperSIMD TM DSP core, enabling real-time UMTS data rates. Results of simulations are presented, showing the number of cycles and amount of memory required, and the data rates supported for various processor clock rates.
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