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Integrating Soft DSP Cores into a SoC

Semiconductor Intellectual Property (SIP) is a blueprint, which can be used as a building block in a chip design. The use of SIP provides the capability for the IP integrators to focus on their area of specialty. SIP DSP cores are broadly used in highly integrated System-on-a-Chip (SoC) designs. Recently, SIP vendors have began to offer synthesizable DSP cores, also referred to as 'soft IP cores', written in HDL code, making the design, technology and EDA tools independent. A soft DSP core allows reuse of the HDL code across multiple foundries and process geometries without the need for costly and timely verification procedures and physical implementations. A reusable soft IP design is not just a matter of HDL writing style. It is a collection of design flow and verification methods that should be taken into consideration in order for the integrator to benefit from a 'soft IP core'. This paper elaborates on the benefits of a soft DSP core and on the IP delivery, which allows it to be efficiently re-used in SoC designs.

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