The use of high-speed I/O in almost every ASIC design requires careful design consideration to avoid issues with power and ground noise and coupling between sensitive signals. Spacing constraints and the desire for very dense designs can lead to signal integrity issues within the package. Timing problems due to crosstalk and simultaneous switching outputs will also become more prevalent in packages with high-speed I/O.
Manufacturing yield and adherence to industry-standard specifications can be maximized over the operating environment of a packaged product through simulation and analysis, with respect to the timing budget. Toshiba utilizes numerous extraction and simulation tools and provides the essential mixed-signal design service resources to analyze signal integrity issues prior to tape out.
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