Design Methodologies for Programmable Logic focuses on advanced high-level HDL design techniques for programmable logic. Advanced coding and optimisation techniques for designs created in VHDL or Verilog will be discussed. Using HDLs (hardware description languages) for a programmable logic architecture presents a different set of challenges compared to gate array architectures and this session will explore issues related to the area and/or speed optimisation of datapath and control functions (such as complex counters, arithmetic functions, complex state machines, multipliers, etc.) described in VHDL or Verilog and targeted to various programmable logic architectures. The paper will cover tips and tricks of coding in HDL's for PLD's and FPGA's and will demonstrate common pitfalls and styling issues for HDL's when targeting popular architectures. Examples of when to code technology independent HDL's and when to code technology dependent HDL's will be discussed. Architecture features to avoid or exploit (e.g. RAMS, instantiating IO's or other vendor primitives, using carry chains, special routing resources, set/reset flops) will be explored.
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