Functional Verification with Embedded Checkers

Functional verification is now dominating the design cycle for many complex chips. Earlier and more thorough detection of bugs is critical for time-to-market improvement. One technique that can help is supplementing traditional simulation with embedded checkers that monitor for correct design intent throughout both block-level and chip-level verification. This paper discusses the use of embedded checkers to assist in the functional verification of a dual-CPU PCI bridge case study design.

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