FPGAs have undisputed advantages in flexibility, zero NRE costs, faster time to market and in-system programmability. Their relative disadvantages, compared to an ASIC solution, are in cost, performance and power consumption. Traditionally, ASICs have been used for high volume, low cost devices or applications in which very high performance is required. The move to 90nm technologies has greatly increased the performance and density of FPGAs. At the same time, the soaring cost of reticule sets has made ASIC solutions uneconomic in 90nm for anything but very high volume markets. Although this has narrowed the gap in performance, there is still a significant penalty in silicon area and power dissipation when selecting an FPGA solution.
To address this problem, FPGA vendors are incorporating increasing amounts of ASIC technology with their programmable logic. Embedded hard cores such as multipliers, processors, transceivers and memories account for about 50% of many high specification FPGAs. However, the decision as to what to embed as a hard core is not always a simple one. For applications not using the ASIC function, this is effectively wasted area and adds to the cost of the FPGA.
The flexiMAC hard core embedded into the LatticeSCM 90nm FPGAs offers all the advantages of highly dense ASIC technology (i.e. low cost, low power and high performance), while retaining the flexibility to address different applications.
In essence, the flexiMAC is a simple packet processor core tailored to address standards that exploit the LatticeSC’s high speed serial I/O. Initially, Lattice has developed microcode for 1G Ethernet MAC, 10G Ethernet MAC, PCI Express Data Link layer and Physical layer functions for x1, x2 and x4 lane channels and Advanced Switching Interconnect (ASI) data link layer functions.
The heart of the flexiMAC is a microcoded processor controlling a datapath customized to packet processing functions such as framing, CRC generation and checking, packet parsing, filtering and flow-control. These functions complement the physical layer functions for Serial protocols implemented in the LatticeSC’s embedded SERDES and Physical Coding Sublayer (PCS) blocks.
The flexiMAC is implemented in high density ASIC logic of ~50K gates so it occupies only a very small die area and saves up to 10x the silicon area over a LUT based implementation of the same functions. The area saving is greatest for 10Gbps data rates in which data-path functions such as CRC checking need a 64bit datapath width in order to run on the FPGA fabric, making it very resource intensive. For example, in 10G Ethernet mode there is a resource saving of approximately 6K LUTs.
View Entire Paper | Previous Page | White Papers Search
If you found this page useful, bookmark and share it on: