Fusing Hardware and Simulation Test Bench Development with Virtual Prototyping Techniques
This article was intitally featured in the Soft Copy section of ECN Magazine. Designers are looking for new methods to reduce verification time for both simulation models and hardware prototypes. In many ways both of these environments suffer from the same problems of test vector creation, test coverage, analysis of results, and detection of elusive timing problems. There are many EDA tools and hardware test systems available to help solve these problems in each environment, but in the past there has not been a way to leverage the work done in one environment into the other. In this paper, we propose several techniques that unite the worlds of simulation and hardware verification and which take advantage of strengths offer by each environment.
View Entire Paper | Previous Page | White Papers Search
If you found this page useful, bookmark and share it on:
Embedded Star Newsletter
Don't have time to visit Embedded Star everyday? Then sign up for our free newsletter. We'll send you an email when we have something to share with you. Your email address will be kept confidential and we will not share, sell, or rent it to anyone. You can unsubscribe at any time by clicking a link in the email.
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
