Accurate and early estimation of chip size is critical to an overall project because it affects both financial as well as technical feasibility. If the die has too many pins for example, it may necessitate utilizing a package that is too large for the board. Or if it draws too much power, it may require airflow in a machine without fans. Toshiba's obligation as an ASIC vendor is to help its customers obtain, as accurately as possible, a resolute picture of their end chip. We will review various tradeoffs to ensure our customer puts the right content in the die/package combination. Enabling them to see the implications of their various choices before design-in is vital in evaluating architectural and economic comparisons.
Sizing Falls into Two Categories
1. Pad-limited Sizing: In this type the number of pins required around the die determines the die size and the logic inside does not fill the entire available core area.
2. Core-limited Sizing: This is where the amount of logic on the inside dominates, thereby setting the die size. The I/O on this type of die may be widely spread, or large empty spaces may exist. The ideal die is a combination of the logic and the I/Os closely matching each other.
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