Enabling Low Power Design Within an RTL-to-GDSII Implementation Flow
Creating optimal low-power designs involves making tradeoffs such as timing-versus-power and area-versus-power at different stages of the design flow. Successful power-sensitive designs require engineers to have the ability to accurately and efficiently perform these tradeoffs. In order to achieve this, engineers require access to appropriate low-power analysis and optimization engines, which need to be integrated with - and applied throughout - the entire RTL-to-GDSII flow. This paper first describes the most significant power dissipation and distribution considerations. The requirements for a true low-power design environment that addresses these power considerations throughout the entire RTL-to-GDSII design flow are then introduced.
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