Developing Configurable IP for SOC

Intellectual property has reached its third generation. Hard proprietary cores represent the first generation. The second generation brings the concept of retargetable synthesizable IP. Now a third generation is emerging with configurable IP that minimizes or eliminates the need to perform RTL modifications to meet specific SOC requirements. This paper describes a configurable memory controller core, a common function in SOC architectures, which was developed using two methods for configuring it to the user's requirements.

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