Designs with Multiple Clock Domains: Avoiding Clock Skew and Reducing Pattern Count using DFTAdvisor and FastScan

This white paper discusses DFT and ATPG issues that commonly occur for designs with multiple clock domains. Multiple vs. single clock in test mode and different scan cell structures will be discussed with respect to the different modes of operation in a scan based test. Different pattern generation methods will be discussed with respect to safe operation, pattern count, and test generation runtime.

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